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VHDL school training courses in Chicago, IL (public, in-house or online) | ||||
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VHDL School: TrainingCity USA Venue: Chicago, Denver, Houston, Los Angeles, Milwaukee, Minneapolis, New York, Phoenix, San Diego, Seattle Tel.: 800-381-5654 This 5 day hands on course presents the elements of the VHDL language (with an emphasis on synthesizable features). It concentrates on the language structures of VHDL. The class is very lab intensive with a minimum of 50% of the time spent on lab exercises. These exercises are a combination of small exercises reinforcing the topics in the lecture, and longer exercises that allow the student to work on “real world�problems. |
SystemVision VHDL-AMS Modeling Format: On-site School: Mentor Graphics Education Services Venue: Wilsonville Tel.: 800-345-2308 The SystemVision VHDL-AMS Modeling course was developed to help you develop VHDL-AMS simulation models for your electrical and mechatronic systems. In this course, you will gain proficiency in analog, digital, mixed analog/digital (mixed-signal), and mixed-technology (multi-physics) model building. You will also learn how to simplify model development with the SystemVision Model Generation Tool, which does much of the modeling work for you. In addition, you will learn how to create and modify sy... |
HDL Designer Series Format: On-site School: Mentor Graphics Education Services Venue: Wilsonville Tel.: 800-345-2308 This class teaches you to use HDL Designer Series effectively in your FPGA or ASIC design process. The lecture takes you through the HDL Designer Series design flow. This includes modeling the design with both graphics and text, generating HDL, and then simulating and animating the design to verify behavior. |
VHDL-AMS Format: On-site School: Mentor Graphics Education Services Venue: Wilsonville Tel.: 800-345-2308 In this 3 day class the designer will learn the basics of the VHDL-AMS (IEEE 1076.1) hardware descriptor language and its efficient use for model creation, validation, and design reuse. The class is intended for analog, mixed-signal, and mixed-nature designers who want to discover what advantages high-level modeling brings to the design process. The three days of the class are spent on the basics of the VHDL-AMS language and teaching efficient modeling practices.
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